The present invention relates to semiconductor devices having a transmission line which uses a multilayer interconnect structure.
In recent years, as the processing speeds of semiconductor devices increase, the signals which flow in semiconductor devices tend to have higher frequencies. For transmission of signals at high frequencies, a transmission line must be used.
Japanese Patent Application Publication No. 2007-535825, which corresponds to WO2005/112105, discloses a method for forming a transmission line at the back end of line in the manufacture of semiconductor devices. According to this document, a ground shield for a transmission line is formed in an interconnect layer just under a signal line.
Japanese Patent Publication No. 2008-141474 describes that a silicon substrate and a multilayer interconnect structure above it are used to form a transmission line not for a semiconductor device but as a component for interconnection. According to this document, a ground shield for the transmission line is formed by the silicon substrate.
Japanese Patent Publication No. 2000-269429 discloses that ground planes and transmission lines are formed through a CMOS process. It also discloses that a digital IC is created through a CMOS process and a matching circuit for RFIC is independently formed and these are integrated on a chip.
The present inventors have realized that these techniques have the following problem. When transistors and a transmission line are formed on a chip through a CMOS process, the transistors and transmission line are coupled by interconnect wiring. With the progress in microfabrication, there is a tendency that the resistance of the interconnect wiring is larger, resulting in an increase of loss in the transmission line. It has been thus found that even when loss in the transmission line for coupling between elements such as transistors is decreased, deterioration in characteristics occurs.